E-126 Switchgear & Power Distribution

LV Switchgear Verification & Assembly Lab

Everything an LV assembly has to prove before it is accepted: design verification and routine verification to IEC 61439, the FAT checklist and certificate, fault level and discrimination, temperature rise inside the enclosure, internal arc classes to IEC 61641, clearance and creepage, and forms of separation. Every calculator shows its working and its limits.

IEC 61439 and the withdrawn IEC 60439

Older project specifications still ask for a "Type Tested Assembly". That wording comes from IEC 60439, which has been withdrawn and replaced by the IEC 61439 series. The change is not cosmetic: it moves the question from "is there a certificate" to "is there evidence covering the arrangement actually supplied".

TopicIEC 60439 (withdrawn)IEC 61439 (current)
Series statusIEC 60439-1 to -5. Withdrawn and replaced; still quoted in older project specifications.IEC 61439-1 (general rules) plus a part for each assembly type, for example -2 for power switchgear and -3 for distribution boards.
Core ideaType-Tested Assembly (TTA) and Partially Type-Tested Assembly (PTTA). A panel was either fully type tested or partly tested with some arrangements assessed.TTA and PTTA are gone. Every design is proved by design verification, which may be by testing, by calculation or by satisfying design rules.
Who is responsibleBlurred between the original manufacturer and the panel builder.Split clearly. The original manufacturer owns the verified design. The assembly manufacturer builds to it and takes responsibility for the finished assembly.
Verification methodsTesting, with limited scope for assessment by comparison.Three routes are recognised and each verification area states which are allowed: testing, calculation or measurement, and satisfying design rules.
DocumentationType test certificates.A design verification file, plus routine verification records for every assembly built.
Temperature riseType test, or extrapolation within set limits.Testing, derived from a tested reference design by calculation, or by calculation to IEC 61439-1 Annex O and P methods.
What a reviewer asks forType test certificate for the assembly.Design verification evidence from the original manufacturer that covers the actual arrangement, plus the panel builder routine test records.
Why it matters on sitePanels were sometimes accepted on a certificate for an arrangement that differed from the one supplied.Evidence must cover the arrangement actually built, which is why the assembly manufacturer declaration matters as much as the certificate.

The three verification routes

Testing

A sample is tested in a laboratory. Required for dielectric properties, short-circuit withstand and mechanical operation.

Calculation or measurement

Derived from a tested reference design, within defined limits. Common for temperature rise and short-circuit withstand of a variant.

Design rules

Satisfying the rules in the standard. Used for clearances, creepage, terminals and the incorporation of devices.

Every one of the twelve design verification areas in tab 2 states which routes are allowed for it. You cannot choose freely: dielectric and short-circuit withstand must be tested.

Where IEC 61641 sits

IEC/TR 61641 is a technical report, not a part of IEC 61439. It gives a method for testing an assembly under internal arcing conditions and the arcing classes A, B and C. An assembly can be fully compliant with IEC 61439 and have no internal arc classification at all, which is why consultants state it separately in the specification. See tab 7.

Two parts you will meet most often

IEC 61439-1
General rules. Applies to every assembly and holds the verification requirements.
IEC 61439-2
Power switchgear and controlgear assemblies. Main boards, MDBs and SMDBs.
IEC 61439-3
Distribution boards intended to be operated by ordinary persons. Final distribution boards.
IEC 61439-4
Assemblies for construction sites.
IEC 61439-5
Assemblies for power distribution in public networks.
IEC 61439-6
Busbar trunking systems. See the Busbar Riser Guide, E-101.

Design verification: the twelve areas

These prove that the design complies with IEC 61439. They are the responsibility of the original manufacturer, and the evidence must cover the arrangement actually supplied. Open each area to see what is verified, how, what to ask for, and what tends to go wrong on site.

12 verification areas TestCalculationDesign rules
AStrength of materials and partsTestDesign rules

What is verified

  • Resistance to corrosion
  • Properties of insulating materials, thermal stability
  • Resistance to abnormal heat and fire from internal electrical effects
  • Resistance to ultraviolet radiation, for outdoor enclosures
  • Lifting, mechanical impact, marking

What to ask for in the submittal

Material declarations, glow wire and ball pressure results, UV data for outdoor enclosures, and the impact rating (IK code).

Site observation

Outdoor panels in hot climates are where UV and heat properties actually bite. Ask for the UV evidence whenever an enclosure sits outside.

BDegree of protection of enclosuresTestDesign rules

What is verified

  • IP rating verification for the installed condition
  • IK impact rating where specified

What to ask for in the submittal

IP test evidence for the enclosure family, and confirmation that gland plates, vents and door seals as supplied do not reduce the rating.

Site observation

A panel is often verified at IP54 then fitted with ventilation louvres on site, which drops the real rating. Check what was added after the certificate.

CClearances and creepage distancesTestDesign rules

What is verified

  • Clearance in air between live parts and to earth
  • Creepage distance across surfaces, by pollution degree and material group

What to ask for in the submittal

Dimensioned busbar arrangement showing the achieved clearance and creepage against the rated impulse withstand voltage and pollution degree.

Site observation

The tightest points are usually at busbar supports, at cable terminations and where links or droppers are added for a project. See tab 8.

DProtection against electric shock and integrity of protective circuitsTestDesign rules

What is verified

  • Effective continuity between exposed conductive parts and the protective circuit
  • Short-circuit withstand strength of the protective circuit

What to ask for in the submittal

Continuity test results for doors, gland plates and removable parts, and the PE conductor sizing basis.

Site observation

Hinged doors with only a paint-to-paint contact fail this. Look for a bonding strap on every door and removable cover.

EIncorporation of switching devices and componentsDesign rules

What is verified

  • Devices installed and operated as the device manufacturer requires
  • Clearances around devices, mounting orientation, and derating respected

What to ask for in the submittal

Device data sheets and the assembly manufacturer confirmation that mounting and spacing follow them.

Site observation

A common issue is a breaker mounted in an orientation or spacing the maker does not allow, which quietly voids its rating.

FInternal electrical circuits and connectionsDesign rules

What is verified

  • Selection and routing of internal conductors
  • Connections, including bolted joints and torque
  • Rated diversity factor applied correctly

What to ask for in the submittal

Internal wiring schedule, conductor sizes, and the torque values used for bolted connections.

Site observation

Torque records are the single most useful piece of paper here. Joints that were never torqued show up later as hot spots on a thermal scan.

GTerminals for external conductorsDesign rules

What is verified

  • Terminal type, size and quantity for the specified external cables
  • Space for bending radius and gland entry

What to ask for in the submittal

Terminal schedule against the project cable schedule, including any parallel runs.

Site observation

Parallel cable runs are frequently missed. A terminal sized for one 240 mm2 cable will not take two.

HDielectric propertiesTest

What is verified

  • Power frequency withstand voltage
  • Impulse withstand voltage, where required

What to ask for in the submittal

Dielectric test evidence for the design, and the routine dielectric result for the panel supplied.

Site observation

Design verification proves the design. The routine test on each panel is the one that catches a damaged or contaminated assembly. See tab 3.

ITemperature rise limitsTestCalculationDerivation

What is verified

  • Temperature rise of busbars, terminals, handles and accessible surfaces
  • Rated diversity factor and ambient conditions used

What to ask for in the submittal

Temperature rise evidence for the arrangement, the ambient it was verified at, and the losses used.

Site observation

Verification ambient is often 35 C while a Dubai plant room runs hotter. Ask what ambient was used and apply the derating. See tab 6.

JShort-circuit withstand strengthTestDerivation

What is verified

  • Rated short-time withstand current Icw and duration
  • Rated peak withstand current Ipk
  • Conditional rated short-circuit current with a specified protective device

What to ask for in the submittal

Icw with its duration, Ipk, and where a conditional rating is used, the exact upstream device it was verified with.

Site observation

A conditional rating is only valid with the named device. Substituting an equivalent breaker invalidates it. See tab 4.

KElectromagnetic compatibilityTestDesign rules

What is verified

  • Emission and immunity for the environment, A or B
  • Segregation of power and control wiring

What to ask for in the submittal

EMC declaration for the environment the panel will be used in, and the internal segregation arrangement.

Site observation

Drives inside a panel are the usual source. Separate control wiring, use screened motor cable and bond screens at both ends through 360 degree glands.

LMechanical operationTest

What is verified

  • Operation of moving parts after installation in the assembly
  • Withdrawable units, interlocks, shutters and door mechanisms

What to ask for in the submittal

Mechanical operation results for the arrangement, typically 200 operating cycles.

Site observation

Test interlocks with the panel in its final arrangement. Doors that bind only once the cables are in are a common late finding.

Design verification proves the design. It does not prove the individual panel in front of you. That is what routine verification in tab 3 is for.

Routine verification and factory acceptance test

Routine verification is carried out on every assembly manufactured, by the assembly manufacturer, before it leaves the works. In practice the consultant or client witnesses it as the factory acceptance test. Tick each item as you witness it, then generate the certificate.

0 of 16 items witnessed

Visual and mechanical

Wiring

Electrical

Dielectric Withstand Verification (Hi-Pot)

Purpose

Verifies the insulation integrity of the switchboard and confirms that live parts are adequately insulated from earth and other conductive parts.

Verification method

A specified test voltage is applied between live conductors and the protective earth circuit for a defined period in accordance with IEC 61439 requirements.

Acceptance criteria

  • No flashover
  • No breakdown of insulation
  • No sustained leakage resulting in test failure

Safety precautions

  • Test to be performed only by qualified and authorised personnel.
  • All equipment must be isolated before testing.
  • Access to the test area must be restricted.
  • Appropriate PPE and insulated test equipment must be used.
  • Stored electrical energy must be safely discharged after completion of the test.
  • Manufacturer and IEC safety procedures must always be followed.

Note: High-voltage dielectric testing can be hazardous if performed incorrectly. This information is provided for educational and verification purposes and is not a substitute for competent testing procedures.

FAT certificate

Fill in the panel data, then generate a certificate carrying your ticks and results. Nothing is sent anywhere; it stays in this browser and prints from your device.

Prospective short-circuit current

The number every switchgear decision depends on. Icw and Ipk ratings, device breaking capacity, discrimination and arc energy all follow from it. This works from the transformer impedance and the cable run to the board, with an allowance for motor contribution.

Inputs

Result

At the board33.4 kA
At transformer38.5 kA
Peak Ipk63.8 kA
X/R3.6
Assembly rating36 kA

A 1600 kVA transformer at 6 % impedance gives about 38.5 kA at its terminals. After 30 m of 2 x 240 mm2 Cu cable the prospective current falls to 31.2 kA, or 33.4 kA with motor contribution.

Transformer impedance
6 mohm (R 0.85, X 5.94)
Cable impedance
1.65 mohm over 30 m
Total impedance
7.41 mohm
Symmetrical Ik
31,170 A
Motor contribution
2,264 A
Peak factor kappa
1.45
Minimum conductor for 1 s
234 mm2 Cu by the adiabatic check
✓
Choose the assembly ratingAn assembly rated 36 kA for 1 s covers 33.4 kA at this point. Check Ipk of 63.8 kA against the rated peak withstand current as well.
✓
Peak current mattersIpk is 63.8 kA, which is what the busbar supports and the protective circuit have to survive mechanically, not the rms value.
i
Conditional ratingsIf the assembly uses a conditional short-circuit rating, it is only valid with the exact upstream device it was verified with. Substituting an equivalent breaker voids it.
i
Confirm the source dataTransformer impedance and X/R come from the test certificate for the actual unit, not from a typical value. Ask the utility or the transformer supplier.

2D: where the fault level falls along the route

Assembly rated 50 kA Transformer 40.8 kA Board 33.4 kA 0 m 30 m Prospective current kA

3D: the assembly and its rating

Drag to orbit, pinch or use + and − to zoom
50 ms · 47.34 kA

Fault level along the cable route, and the clearing window at the board.

Assumptions and limits

Method
Three-phase symmetrical short-circuit current from the transformer impedance in series with the cable impedance, after IEC 60909.
Transformer
Zt = U squared divided by S, times the percentage impedance. Split into R and X by the X/R ratio you enter.
Cable
Resistance from standard conductor values at 20 C, reactance taken at 0.08 ohm per km. Parallel runs divide the impedance.
Peak current
Ipk = kappa x root 2 x Ik, with kappa = 1.02 + 0.98 exp(-3 R/X).
Motor contribution
A simple multiple of motor full-load current, added to the symmetrical current. Set it to zero to exclude motors.
Not included
Network impedance upstream of the transformer, which reduces the result slightly, and any current limiting from upstream devices.

Curve study: how a protection curve works

Every discrimination argument, every cable protection check and every arc energy figure rests on a time-current curve. This section takes one apart, lets you move the settings and watch the curve respond, shows what the breaker is doing physically, and plays a fault through from start to clearance.

1. Anatomy of a curve

Select a region of the curve to read what it does. The highlighted band follows your selection.

1x2x5x10x20x50x100x200x0.01 s0.1 s1 s10 s1 min10 min1 h Thermal Short time Instantaneous Current as a multiple of In Operating time
Thermal region, long time: A bimetal strip heats and bends, or an electronic unit integrates current over time. The higher the current the faster it operates, following roughly an inverse square law. This region protects the cable against overload.

2. Device explorer

Change the family and the settings. The curve redraws live, and the marker shows how long the device would take to trip at your test current.

MCCB, electronic trip unit (LSI): Long time, short time and instantaneous elements, each adjustable. The short time delay is what makes discrimination possible with a downstream device.

At your test current

Trip time10 ms
Multiple of In10 x
RegionInstantaneous
Let-through0.1 MA2s
✓
Does it trip at all2,500 A is 10 times In and lands in the instantaneous (magnetic) region.
✓
Clearing time10 ms is within the usual expectation for this region.
✓
Short time elementA 0.2 s delay above 1,500 A lets a downstream device clear first. This is what makes discrimination possible.
i
Tolerance bandThe real device operates somewhere inside the shaded band, not on the line. Never claim discrimination from curves that merely touch.
1k10k0.01 s0.1 s1 s10 s1 min10 min1 h Test 2,500 A 10 ms Current (A, log scale) Operating time (log scale)

The shaded band is the tolerance band. The dashed vertical line is your test current. Settings that do not apply to the selected family are ignored and the field is greyed.

3. What happens inside the breaker

The same test current, shown physically. The bimetal strip bends as heat builds in the thermal region. The solenoid pulls instantly in the magnetic region. Watch which one acts first.

Drag to orbit. The mechanism animates at your test current.

4. The fault, played out in time

Press play. The current rises, the trip element decides, the contacts part, the arc draws and clears at the next current zero. The shaded area is the let-through energy the cable and the assembly have to survive.

20 ms · 0 kA

The fault current, the trip decision and the arc clearing, in milliseconds.

Fault occurs

0 ms

Current rises within the first half cycle, limited only by the circuit impedance.

Trip element decides

10 ms

The solenoid reaches pickup and releases the latch immediately.

Contacts part

13 ms

Mechanical opening takes a few milliseconds after the decision. An arc draws between the contacts.

Arc clears

23 ms

The arc is driven into the splitter plates and extinguishes at a current zero. Everything up to this moment is let-through energy.

5. Reading a manufacturer curve on the job

i
Check the axes firstMost published curves use multiples of In on the horizontal axis, not amperes. A curve that looks identical for a 32 A and a 250 A device is plotted in multiples.
i
Find the tolerance bandIf the sheet shows a single line, it is a nominal curve. Ask for the band before using it for any discrimination argument.
i
Look for the cold and hot curvesA device that has been carrying load trips faster than one starting cold. Published curves usually state which condition they represent.
i
Note the temperature basisMCB curves are usually given at 30 C. In a 45 C panel the thermal element trips earlier, which affects both nuisance tripping and discrimination.
i
Separate the trip curve from the let-through curveThe trip curve says when the device decides. The let-through curve says how much energy actually passes. Current limiting devices clear far less energy than their trip curve suggests.
i
Check the breaking capacityIcu is the ultimate breaking capacity, Ics the service value. A device may survive Icu once and be unfit for further service, which is why Ics matters for main boards.

Assumptions and limits

Thermal region
An inverse curve of the form t = K divided by (x squared minus 1), with x the multiple of the long time setting. K is chosen so the shape matches typical published MCB and MCCB curves.
Short time region
A flat band at the set delay, applied above the short time pickup. Available on electronic trip units only.
Instantaneous region
A flat band at about 10 milliseconds above the instantaneous pickup, which is the usual mechanical opening time.
Tolerance band
Drawn at plus and minus 20 per cent on current in the thermal region and plus and minus 20 per cent on the magnetic pickup, which is the usual order for published bands.
What this is not
A substitute for the manufacturer curve for the actual device. Use it to understand behaviour and to screen settings, then confirm against the published curve and selectivity tables.

Discrimination between two devices

A fault on a final circuit should trip only its own device. This draws both time-current curves, finds where they meet, and tells you what that means at your fault level. It is a teaching and screening tool, not a substitute for the manufacturer selectivity tables.

Devices

Result

DiscriminationHolds
Crossovernone found
Current ratio6.4
Fault level35 kA

On these simplified curves the ACB 1600 A and MCCB 250 A keep discrimination up to the 35 kA fault level. Confirm with the manufacturer selectivity table.

✓
Current ratioUpstream 1600 A against downstream 250 A is a ratio of 6.4. A ratio below about 1.6 rarely gives discrimination in the overload region.
✓
Magnetic settingsUpstream magnetic pickup 12,800 A against downstream 2,500 A. The upstream setting should sit clearly above the downstream one.
✓
Short-time delayUpstream short-time delay of 0.2 s holds the upstream device back while the downstream device clears.
✓
Discrimination limitNo crossover found up to the fault level of 35 kA on these simplified curves.
i
Confirm with the manufacturerTime-current curves alone do not prove discrimination at high currents. Energy let-through and dynamic behaviour decide it, so always check the manufacturer selectivity tables for the exact device pair.

2D: time-current curves

101001k10k0.01 s0.1 s1 s10 s1 min10 min1 h Prospective fault 35 kA Current (A, log scale) Operating time (log scale) Upstream Downstream

Upstream in amber, downstream in cyan. Where the amber curve drops to or below the cyan curve, both devices can operate for the same fault.

Assumptions and limits

Thermal region
An inverse curve of the form t = K divided by (x squared minus 1), with x the multiple of In. K differs between MCB and MCCB to match typical published curves.
Magnetic region
A flat band at the instantaneous time, or at the short-time delay where one is set on the upstream device.
What this cannot show
Energy let-through, dynamic behaviour, current limiting and the published selectivity limit current Is. At high fault currents these decide the outcome, not the curves.
Use it for
Spotting obvious problems early: ratings too close together, magnetic settings overlapping, no short-time delay on an upstream device.
Always confirm the final pair against the manufacturer selectivity tables. A pair that looks selective on curves can still fail at high current, and a pair that looks poor on curves can be fully selective through current limiting.

Enclosure temperature rise

Device losses raise the air temperature inside the assembly. If the internal temperature exceeds what the devices were verified for, their ratings no longer apply. This follows the IEC 60890 calculation method, which is one of the routes IEC 61439 allows for verifying temperature rise.

Enclosure and load

Result

Top of enclosure85 C
Average inside76 C
Rise at top39.9 K
Cooling surface5.07 m2
Loss density237 W/m2

With 1,200 W of losses in a 800 x 2000 x 600 mm enclosure at 45 C ambient, the top of the enclosure reaches about 85 C, a rise of 39.9 K.

Effective cooling surface Ae
5.07 m2
Factor k
0.1025
Exponent x
0.804 (not vented)
Distribution factor d
1.3
Average rise
30.7 K
Rise at the top
39.9 K
Airflow to hold the limit
149 m3/h
!
Internal temperatureTop of enclosure reaches about 85 C against a limit of 70 C, from 45 C ambient plus a rise of 39.9 K.
!
Loss density1,200 W over 5.07 m2 of effective cooling surface is 237 W/m2. Above roughly 180 W/m2 a plain enclosure usually needs forced ventilation or cooling.
i
If the limit is exceededForced ventilation of about 149 m3/h would hold the rise, or fit a cooling unit sized for 1,200 W. Derating the devices is the alternative.
i
Check the verification ambientCompare this result with the ambient the assembly was verified at. A panel verified at 35 C placed in a 45 C plant room needs the device ratings checked against the maker derating tables.

3D: where the heat sits

Drag to orbit. Colour follows temperature, hottest at the top.
12:00 · 83.83 C

A working day load profile and the internal temperature that follows it.

Typical loss figures to start from

ItemTypical lossesNote
ACB, 1600 A frame250 to 400 WRises with the square of the load current
MCCB, 250 A frame30 to 60 WPer device at full load
MCB, 63 A5 to 10 WAdds up quickly in a dense board
Busbar, per metre30 to 120 WDepends on cross-section and loading
Contactor, 100 A10 to 25 WCoil plus contact losses
VFD, 30 kW700 to 1200 WThe usual reason a panel needs cooling
Control transformer, 500 VA25 to 50 WContinuous

Always use the device manufacturer loss figures for the actual devices and the actual loading. The values above are only a starting point when the data sheets are not yet available.

Assumptions and limits

Method
IEC 60890: effective cooling surface Ae from the enclosure faces with their installation factors, then temperature rise = d x k x P to the power x.
Exponent x
0.804 for an enclosure without ventilation openings, 0.715 with openings.
Factor d
1.0 up to 1800 mm height, 1.3 above it, which accounts for the hotter air at the top of a tall enclosure.
Surface factors
The bottom face is not counted. A face against a wall or an adjacent panel contributes about half as much as a free face.
Ventilation estimate
Airflow is approximated as 3.1 x losses divided by the allowable rise. Use the fan or cooling unit maker data for the final selection.
Not included
Solar gain on outdoor enclosures, heat from adjacent equipment, and non-uniform loading within the panel.

Internal arc and IEC 61641

IEC/TR 61641 is a technical report, separate from IEC 61439. It defines how an assembly is tested under internal arcing conditions and sets out the arcing classes. Consultants state it in the specification because an assembly can be fully IEC 61439 compliant with no arc classification at all.

The five evaluation criteria for Arcing Class A, personnel protection

1
Doors and covers remain closed and secured during the test.
2
No hazardous parts are ejected from the assembly.
3
No holes develop in accessible external surfaces below 2 m due to burning.
4
Cotton indicators do not ignite from arc products.
5
Protective circuit continuity remains effective after the test.
Class A

Personnel protection

Criteria 1 to 5 are satisfied.

What it means in practice: People standing in front of the assembly are protected during the arc event. The assembly itself may be destroyed.

Class B

Limited arc propagation

Criteria 1 to 5, and the arc remains confined to the compartment or area where it started and does not propagate to other sections.

What it means in practice: Damage is contained, so the rest of the board is far more likely to be recoverable.

Class C

Continued limited operation

Criteria 1 to 6, and after fault clearing and isolation of the affected section, limited operation of the remaining assembly is still possible.

What it means in practice: Essential circuits elsewhere in the board can be brought back without a full rebuild.

Specification wording builder

State the classification, the test current, the duration and which faces are accessible. Build the line here and copy it into your specification.

Specification line

Internal Arc Tested in accordance with IEC/TR 61641, Class B, 65 kA for 0.5 sec, Front and Side Accessible.

Indicative incident energy

Arcing class protects people standing in front of a closed assembly during the test. Incident energy is a different question: how much thermal energy reaches a worker at a given distance. This gives an indication of the scale.

Result

Incident energy17.8 cal/cm2
Arcing current20 kA
Boundary2,837 mm
Clearing0.2 s

A 38 kA bolted fault cleared in 0.2 s gives roughly 17.78 cal/cm2 at 455 mm. Up to about 25 cal/cm2.

!
Incident energyAbout 17.78 cal/cm2 at 455 mm working distance for a 0.2 s clearing time. Up to about 25 cal/cm2.
✓
Clearing timeClearing time drives the result almost in proportion. Reducing 0.2 s to half would roughly halve the energy. Arc reduction or maintenance switching settings are the usual lever.
i
Arc flash boundaryEnergy falls to about 1.2 cal/cm2 at roughly 2,837 mm from the arc.
i
This is an indication onlyA real arc flash study uses the actual protection settings, the verified arcing current range and the site configuration. Use a study by a competent engineer for labelling and procedures.
8 cal/cm2 1.2 cal/cm2 Your clearing time: 17.8 cal/cm2 0.05 s1.0 s cal/cm2
140 ms · 12.28 cal/cm2

Energy building up during the arc, and the moment protection clears it.

Assumptions and limits

Method
IEEE 1584 empirical equations for an arc in an enclosure at low voltage, with a distance exponent of 1.473 for switchgear.
Clearing time
Entered directly. It is the single strongest influence on the result, close to proportional.
Not included
Arcing current variation, the actual protection settings and their tolerance, system configuration and the arc flash boundary for every scenario.
Use it for
Understanding the scale of the hazard and the effect of clearing time. Not for labelling, procedures or PPE selection.
Arc flash labelling, work procedures and PPE selection must come from a study carried out by a competent engineer using the actual protection settings and system configuration.

Clearance and creepage distances

Clearance is the shortest distance through air between two conductive parts. Creepage is the shortest distance along the surface of the insulation between them. Both are verified by design rules, which is why dimensioned drawings matter more than certificates here.

2D: the difference, shown

Insulating barrier or support Live part Earthed part Clearance: straight through air Creepage: along the surface, including into any groove A groove or rib lengthens the creepage path without needing more space

Minimum clearance in air

By rated impulse withstand voltage, pollution degree 2, inhomogeneous field.

Rated impulse UimpMinimum clearance
2.5 kV1.5 mm
4 kV3.0 mm
6 kV5.5 mm
8 kV8.0 mm
12 kV14.0 mm

Pollution degrees

PDCondition
1No pollution or only dry non-conductive pollution. Sealed assemblies only.
2Normally only non-conductive pollution, with occasional temporary condensation. The usual case for indoor LV assemblies.
3Conductive pollution, or dry non-conductive pollution that becomes conductive through condensation. Industrial and some outdoor conditions.
4Continuous conductive pollution from dust, rain or snow. Outdoor assemblies without protection.

Minimum creepage by insulation material group

Material group I is the best tracking performance, group IIIa the poorest of those shown. Most moulded panel insulation falls in group II or IIIa.

Working voltagePollutionGroup IGroup IIGroup IIIa
250 VPollution degree 21.8 mm2.5 mm2.5 mm
400 VPollution degree 22.0 mm2.8 mm3.2 mm
500 VPollution degree 22.5 mm3.6 mm4.0 mm
690 VPollution degree 23.2 mm4.5 mm5.0 mm
400 VPollution degree 33.2 mm4.0 mm4.0 mm
690 VPollution degree 35.0 mm6.3 mm6.3 mm

Values below are the usual starting points for verification. Always confirm against IEC 60664-1 and IEC 61439-1 for the actual rated impulse withstand voltage, pollution degree and insulation material group.

Where it goes wrong on site

!
Project links and droppersBusbar links added for a specific project are the most common place clearance is lost, because they are fabricated outside the verified arrangement.
!
Cable lugs and terminationsLarge lugs on adjacent phases close the gap. Check the clearance with the actual lug, not the terminal.
!
Condensation and dustA panel verified at pollution degree 2 that sits in a dusty or humid plant room is effectively operating at degree 3. The required creepage goes up.
i
What to ask forA dimensioned busbar and termination drawing showing achieved clearance and creepage against the rated impulse withstand voltage and the pollution degree.

Forms of internal separation

The form describes how far the assembly separates busbars, functional units and terminals from each other. It decides what maintenance is possible with the rest of the board live, which is why it appears in almost every specification.

2D: the seven forms

Busbars Unit 1 Terminals Unit 2 Terminals Unit 3 Terminals Unit 4 TerminalsSolid outline: a barrier is present. Dashed outline: no separation at that boundary.

Form 4b: Full separation, with terminals in a separate compartment from their functional unit. The highest common requirement for MCCB boards. Maintenance on one circuit can proceed with the rest live, which is why consultants specify it for main boards.

FormSeparationWhat it means for maintenance
Form 1No internal separation.Busbars, functional units and terminals share one space. Work on any part needs the whole assembly dead.
Form 2aBusbars separated from functional units. Terminals not separated from busbars.The busbar system is protected from accidental contact during work on a functional unit, but the terminals remain in the busbar space.
Form 2bBusbars separated from functional units. Terminals separated from busbars.Cable terminals sit in their own protected area, so cable work does not expose the busbars.
Form 3aBusbars separated from functional units, and functional units separated from each other. Terminals not separated from busbars.Work on one outgoing way does not expose the next, but terminals are still in the busbar space.
Form 3bBusbars separated from functional units, functional units separated from each other, and terminals separated from busbars but not from each other.The usual choice for many distribution boards. Cable terminals are protected from the busbars but share one terminal space.
Form 4aFull separation, with terminals in the same compartment as their functional unit.Each outgoing way is a compartment with its own terminals inside it.
Form 4bFull separation, with terminals in a separate compartment from their functional unit.The highest common requirement for MCCB boards. Maintenance on one circuit can proceed with the rest live, which is why consultants specify it for main boards.

Choosing a form

Final distribution boards
Form 2b is common and often sufficient, since maintenance is usually done with the board isolated.
Sub-main boards
Form 3b is the usual choice, giving separation between outgoing ways and protected terminals.
Main boards and MCCB panels
Form 4b is widely specified, so one circuit can be worked on with the rest of the board live.
What the form does not do
A high form does not make the assembly arc resistant. Internal arc classification is a separate matter, covered in tab 7.
Cost and size
Each step up in form adds barriers, compartments and width. Specify what the maintenance strategy actually needs.

Guide to this lab

What each tool does, what to type into it, the formulas behind it, a worked example, and where it stops being reliable.

What this lab does and when to use it

It covers the evidence an LV assembly has to produce before it is accepted, and the calculations that decide whether the assembly is right for its position in the installation.

  • Reviewing a switchgear submittal: tabs 1, 2, 8 and 9. Check that the verification evidence covers the arrangement offered, and that the form of separation and the clearance data match the specification.
  • Preparing for or witnessing a FAT: tab 3. Work down the checklist as you witness, then generate the record.
  • Sizing or checking a board: tabs 4, 5 and 6. Fault level first, then discrimination, then whether the enclosure can lose the heat.
  • Writing a specification: tabs 7 and 9, which produce the internal arc line and the form of separation choice.

Inputs, units, formulas and assumptions

Fault level, tab 4

Transformer rating
kVA. From the nameplate.
Impedance Z
Per cent. From the transformer test certificate, not a typical value.
X/R ratio
Dimensionless. Typically 6 to 10 for distribution transformers. It sets the peak factor.
Cable size, length, runs
mm2, m, number. The route from transformer to the board in question.
Formula
Zt = U squared / S x Z per cent. Ik = U / (root 3 x Z total). Ipk = kappa x root 2 x Ik with kappa = 1.02 + 0.98 exp(-3 R/X).

Discrimination, tab 5

In
Rated current of each device in amperes.
Magnetic pickup
As a multiple of In. From the device setting or its published curve.
Short-time delay
Seconds. Only upstream devices with a short-time function have one.
Formula
Thermal region t = K / (x squared minus 1) where x is I/In. Magnetic region is a flat band at the instantaneous or short-time delay.

Temperature rise, tab 6

Enclosure dimensions
mm. External dimensions of the enclosure.
Installation
Which faces are free to dissipate heat. A face against a wall contributes about half.
Total device losses
Watts, at the actual loading. From the device data sheets.
Formula
IEC 60890: dT = d x k x P to the power x. x is 0.804 without vents and 0.715 with. k falls as the effective cooling surface Ae grows. d is 1.3 above 1800 mm height.

Internal arc, tab 7

Prospective fault current
kA. From tab 4.
Electrode gap
mm. Typically 32 mm for LV switchgear, 25 mm for panelboards.
Clearing time
Seconds. The total time for protection to clear the arc, which dominates the result.
Working distance
mm. 455 mm is the usual LV switchgear working distance.
Formula
IEEE 1584 empirical equations for an arc in a box, with a distance exponent of 1.473.

Worked engineering example

The situation. A 1600 kVA transformer at 6 per cent impedance feeds a main board through 30 m of two parallel 240 mm2 copper cables. There are 300 kW of motors on the board. The board sits against a wall in a plant room that reaches 45 C. The devices dissipate about 1200 W.

Step 1, fault level. Transformer impedance is 400 squared divided by 1,600,000, times 0.06, which gives 6.0 milliohms. At the terminals that is 38.5 kA. After the cable the symmetrical current falls to about 31 kA, and motor contribution adds roughly 2 kA, so the board sees about 33 kA. Peak current is about 64 kA. An assembly rated 50 kA for 1 second covers it with margin.

Step 2, discrimination. A 1600 A ACB upstream of a 250 A MCCB gives a current ratio of 6.4, which is comfortable. With a 0.2 second short-time delay set on the ACB, the simplified curves show no crossover up to the fault level. That is a promising result, but the pair still has to be confirmed against the manufacturer selectivity table, because at 33 kA the outcome depends on energy let-through rather than on the curves.

Step 3, temperature rise. An 800 by 2000 by 600 mm enclosure against a wall has an effective cooling surface of about 5.1 m2. With 1200 W of losses the top of the enclosure rises about 40 K above ambient. At 45 C ambient that is 85 C inside, which is above a 70 C limit. Forced ventilation of roughly 150 m3/h would hold the rise, or the devices need derating against the maker tables. This is the step most often skipped, and it is why panels verified at 35 C misbehave in a hot plant room.

Step 4, internal arc. At 33 kA with a 0.2 second clearing time the indicative incident energy at 455 mm is in the region of 15 cal per square centimetre. Halving the clearing time roughly halves it, which is why an arc reduction or maintenance setting is worth more than any amount of PPE. The specification line for the assembly would read: Internal Arc Tested in accordance with IEC/TR 61641, Class B, 65 kA for 0.5 sec, Front and Side Accessible.

Practical site observations and common mistakes

  • A certificate for a different arrangement. The most common submittal problem. Design verification evidence has to cover the arrangement actually supplied, not a similar one from the same family.
  • Conditional ratings quietly broken. A conditional short-circuit rating is valid only with the named upstream device. Equivalent breakers from another maker void it.
  • Verification ambient ignored. A panel verified at 35 C in a 45 C plant room is already outside its basis before a single device is loaded.
  • Torque never recorded. Joints that were never torqued appear months later as hot spots on a thermal scan. Ask for the torque values and the calibration certificate of the wrench.
  • Door bonding by paint. A hinged door needs a bonding strap. Paint-to-paint contact fails the protective circuit continuity test.
  • Ventilation louvres added after the IP evidence. The real IP rating drops, and nobody updates the paperwork.
  • Parallel cable runs at terminals. Terminals sized from a single-cable schedule will not take two cables per phase.
  • Discrimination assumed from ratings alone. A 1.25 ratio between devices almost never discriminates. Check the tables.

Calculation limitations

  • Fault level excludes network impedance upstream of the transformer, so the real figure is slightly lower. It also excludes current limiting from upstream devices.
  • Discrimination is drawn from simplified curves. It cannot represent energy let-through, dynamic behaviour or the published selectivity limit current, which decide the outcome at high fault currents.
  • Temperature rise assumes uniform loss distribution and no solar gain. Outdoor enclosures and panels with a single large heat source need the detailed method or a supplier calculation.
  • Incident energy is an indication of scale. Labelling, procedures and PPE must come from a study using actual settings.
  • Clearance and creepage tables are starting points. The verified values come from the assembly manufacturer design file against the actual impulse withstand voltage and pollution degree.

Standards referenced in this lab

IEC 61439-1
General rules for low-voltage switchgear and controlgear assemblies, including design and routine verification.
IEC 61439-2
Power switchgear and controlgear assemblies.
IEC 61439-3
Distribution boards intended to be operated by ordinary persons.
IEC 60439 series
Withdrawn and replaced by IEC 61439. Still quoted in older specifications.
IEC/TR 61641
Guide for testing under conditions of arcing due to internal fault, and the arcing classes.
IEC 60890
Method of temperature rise verification by calculation.
IEC 60909
Short-circuit current calculation in three-phase AC systems.
IEC 60664-1
Insulation coordination: clearances, creepage distances and pollution degrees.
IEC 60947-2
Circuit breakers, including selectivity and conditional ratings.
IEEE 1584
Guide for performing arc flash hazard calculations.

Engineering review notes

Three things decide whether a switchgear submittal is sound, and none of them is the certificate on the front page.

  1. Does the evidence match the arrangement? Compare the verified arrangement against the general arrangement drawing offered. Differences in busbar run, compartment layout or device mix are what invalidate the evidence.
  2. Does the rating suit the position? Icw and its duration, Ipk, and any conditional rating with its named device, all checked against the fault level at that board rather than at the transformer.
  3. Will it survive its environment? Verification ambient against plant room ambient, IP rating against the actual installed condition, and pollution degree against what the room is really like.

Everything on this page is a planning and review aid. Confirm every figure against current manufacturer data and the authority requirements that apply to your project before design sign-off.

About this lab: LV Switchgear Verification & Assembly Lab

LV Switchgear Verification & Assembly Lab: IEC 61439 Design and Routine Verification

Work through what an LV assembly must prove before energisation: the twelve design verification areas of IEC 61439, the routine verification and factory acceptance tests carried out on every panel, prospective fault level, protection discrimination, temperature rise inside the enclosure, internal arc classification to IEC 61641, clearance and creepage, and forms of separation.

Topics you can explore

  • IEC 61439 compared with the withdrawn IEC 60439 series
  • Design verification by testing, calculation and design rules
  • Routine verification and the FAT certificate for every panel
  • Prospective short-circuit current from transformer and cable data
  • Time-current discrimination between upstream and downstream devices
  • Enclosure temperature rise and ventilation to IEC 60890
  • Internal arc classes A, B and C and the specification wording
  • Clearance, creepage and forms of separation 1 to 4b

Practical engineering example

A 1600 kVA transformer at 6 % impedance gives roughly 38 kA of prospective short-circuit current at its terminals, so an assembly rated 50 kA for 1 second is suitable at the main board, while the fault level falls along each cable run and allows lower rated devices further downstream, provided the selectivity tables confirm the device pair.

Developed by Eng. Mannan Maqsood. Verify design outputs against current project requirements and the applicable authority and manufacturer data.

© 2026 Eng. Mannan Maqsood | Engineering Excellence Through Interactive Labs

VERIFY ALL FIGURES AGAINST CURRENT MANUFACTURER DATASHEETS AND LOCAL AUTHORITY REQUIREMENTS BEFORE DESIGN SIGN-OFF.